A series of processes, which coat a substrate, such as a semiconductor device and an LCD substrate, with a resist liquid, and develop the substrate after the resist has been developed with a predetermined pattern, so as to form a desired resist pattern on the substrate, are generally performed by a system in which an exposure apparatus is connected to a coating and developing apparatus that performs a resist-liquid coating process and a developing process. The system is composed by linearly arranging: a carrier block on which a wafer cassette accommodating a substrate such as a semiconductor wafer (herein after referred to as “wafer”), the carrier block having a transfer arm that transfers a wafer to and from the wafer cassette; a process block that performs a resist-liquid coating process and a developing process on a wafer transferred from the carrier block; and an interface block that connects the process block and an exposure apparatus with each other.
Wafers on which a resist pattern has been formed are subjected to a predetermined inspection which inspects a line width of the resist pattern, an overlapping condition of the resist pattern and a base pattern, and a developing defect. Then, only the wafers accepted by the inspection are subjected to a succeeding process. At this time, since an inline system in which an inspection module is disposed in a coating and developing apparatus is easy to use, the present inventors adopt a structure, as shown in FIG. 10, in which an inspection block B2 including a plurality of inspection modules 11 is interposed between a carrier block B1 and a process block B3. In FIG. 10, the reference numbers B4 and B5 depict an interface block and an exposure apparatus, respectively.
In such a system, wafers in a wafer cassette 10 are transferred from the carrier block B1 to the process block B3 through the inspection block B2 without stopping thereat. After the wafers has been subjected to a resist-liquid coating process in the process block B3, the wafers are transferred through the interface block B4 to the exposure apparatus B5, and subjected to a predetermined exposure process by the exposure apparatus. The exposed wafers are then subjected to a developing process in the process block B3, and thereafter the wafers are subjected to a predetermined inspection in the inspection block B2. On the other hand, wafers, which are not subjected to an inspection, are developed in the process block B3, and then returned to the carrier block B1 through the inspection block B2 without stopping thereat.
At this time, whether to inspect wafers in a lot or not, and a type of inspection, if an inspection is performed, are previously determined for each lot. In a case in which an inspection is performed, for example, when wafers are taken out from the wafer cassette 10 by a transfer arm (not shown) of the carrier block B1, an inspection reservation signal is outputted from a control part (not shown), which controls the coating and developing apparatus, to an inspection module which will perform the inspection. The inspection module performs an inspection on wafers, whose inspection reservation signals have been received, in the order of the receipt of the inspection reservation signals.
The reason for previously outputting an inspection reservation signal to the inspection module 11 before the wafers are transferred to the inspection module 11 is to facilitate creation of a transfer program. In addition, it takes a predetermined time period for the inspection module to get prepared. Thus, the preparation of the inspection module is made in parallel with a resist-pattern formation process, whereby processed wafers can be inspected immediately after the wafers have been transferred to the inspection block B2. In this manner, a decrease in throughput can be prevented.
If the inspection module 11 has trouble, wafers to be inspected by the inspection module 11 are transferred in a bypassing manner until the trouble of the inspection module 11 is resolved and the inspection module 11 returns to a normal state. To transfer wafers in a bypassing manner herein means to transfer the wafers to a buffer module 12, instead of the inspection module 11, disposed in the inspection block B2 and to transfer the wafers to a destination next to the inspection module, such as the carrier block B1.
When the trouble of the inspection module 11 is resolved, a wafer to be inspected for confirmation is transferred from the carrier block B1 directly to the inspection block B2. Then, the inspection module 11 inspects the wafer for inspection confirmation so as to confirm whether the inspection module 11 is in order or not. After the wafer for inspection confirmation has been inspected by the inspection module 11, the wafer is again returned to the carrier block B1.
However, in the above structure, there is a possibility that, although the trouble of the inspection module 11 has been resolved and the inspection module 11 becomes available, many wafers have not been transferred to the inspection module 11, so that the wafers cannot be subjected to the inspection. This problem is concretely described with reference to FIG. 11. In FIG. 11, the horizontal axis shows a time. The first row of FIG. 11 shows a timing at which wafers are taken out from the wafer cassette 10 in the carrier block B1, and a timing at which the wafers are returned to the wafer cassette 10. The second row of FIG. 11 shows a process condition of the wafers in the inspection module 11, and the third row thereof shows a transfer condition of the wafers to the buffer module 12.
The first row is described at first. Lots A to F respectively accommodate twenty-five wafers. The wafers in the respective lots A to F are inspected by one inspection module 11, and then returned to the carrier block B1 which is a destination next thereto. Time point at a left end of each of the lots A to F is a timing at which a first wafer is taken out from the wafer cassette 10 of each of the lots A to F in the carrier block B1, and a time point at a right end of each of the lots A to F is a timing at which a last wafer of the wafers in each of the lots A to F, which have been subjected to all the processes including the inspection, is returned to the wafer cassette 10. Namely, a time point T1 shows a time point at which a first wafer (A1) of the lot A is taken out from the wafer cassette 10, and a time point T4 shows a time point at which a last wafer (A25) of the lot A is returned to the wafer caste 10. When a first wafer of each of the lots A to F is taken out from the wafer cassette 10, an inspection reservation signal is outputted from the control part to the inspection module 11 intended for performing an inspection to the wafers. Namely, in the lot A, an inspection reservation signal a is outputted at the time point T1 at which the first wafer (A1) is taken out from the wafer cassette 10A.
The second row is described. A time point at a left end of each of the lots A to F corresponds to a time point at which a first wafer in each of the lots A to F is loaded into the inspection module 11, and a time point at a right end of each of the lots A to F corresponds to a time point at which a last wafer in each of the lots A to F is unloaded from the inspection module 11. For example, a time point T2 is timing at which the first wafer (A1) in the lot A is loaded into the inspection module 11, and a time point T4 are a timing at which the last wafer (A25) in the lot A is unloaded from the inspection module 11, and a timing at which a first wafer (B1) in the lot B is loaded into the inspection module 11.
Wafers are transferred to the inspection module 11 by means of a transfer means disposed on the inspection block B2. The transfer means is provided with two arms. An inspected wafer (A25) is taken out by the one arm from the inspection module 11, and a wafer (B1) to be inspected, which is held by the other arm, is continuously transferred to the inspection module 11. Thus, although there is a slight time lag between the timing at which the wafer (A25) is taken out and the timing at which the wafer (B1) is transferred, such a time lag is significantly short. Thus, these timings are shown by the same time point as a matter of convenience. Although a time point T4 corresponds to a time point at which the wafer (A25) is returned to the wafer cassette 10 in the first row, the wafer (A25) taken out from the inspection module 11 is immediately transferred into the carrier block B1. Thus, FIG. 11 shows these time points by the same time point for a matter of convenience. This holds true with the other cases.
A time point T3 is a time point at which the inspection module 11 to be used has a trouble, and a time point T5 shows a time point at which the trouble of the inspection module 11 is resolved and the inspection module 11 becomes available. In this example, in the course of the inspection of the wafers of the lot A, trouble occurs in the inspection module 11.
As described above, when a first wafer of each of the lots A to F is taken out from the wafer cassette 10, an inspection reservation signal is outputted to the inspection module 11. However, when the inspection module 11 has trouble and is unavailable, the control part forbids the output of an inspection reservation signal. Thus, in this embodiment, during an interval between the time point T3 and the time point T5, the inspection module 11 is unavailable because of the trouble. Since a first wafer of the lot D and a first wafer of the lot E are taken out from the wafer cassettes 10 during the trouble, the control part does not output an inspection reservation signal for the lot D and E.
Thereafter, when the trouble of the inspection module 11 is resolved and the inspection module 11 becomes available, a wafer CW for inspection confirmation is brought out from the wafer cassette 10. When this wafer CW for inspection confirmation is brought out from the wafer cassette 10, an inspection reservation signal w for the wafer CW is outputted to the inspection module 11. Thus, the inspection reservation signal w for the wafer CW for inspection confirmation is received by the inspection module 11, with the order of the inspection reservation signal w being next to an inspection reservation signal c for the lot C.
During the time inspection module 11 is unavailable (the time interval between the time point T3 and the time point T5), wafers to be transferred to the inspection module 11 during this time, with inspection reservation signals for the wafers having been outputted to the inspection module 11 before the inspection module 11 has a trouble (i.e., latter wafers of lot A, wafers of lot B, and wafers of lot C), and are ready to be transferred into the inspection module 11. Thus, these wafers are transferred in a bypassing manner to the buffer module 12, instead of the inspection module 11, of the inspection block B2. In this example, the trouble of the inspection module 11 is resolved during the course of taking out the wafers of the lot C. However, the inspection reservation signal c for all the wafers of the lot C has been already outputted, all the wafers of the lot C are transferred to the buffer module 12 in the bypassing manner.
On the other hand, wafers whose inspection reservation signals are not outputted, which are all the wafers of lots D and E, are handled similarly to wafers that are not inspected, and transferred in a skipping manner. To transfer wafers in a skipping manner means that wafers are transferred similarly to a wafer that has not been inspected, and to a destination next to the inspection module 11 (i.e., to the carrier block B1 for example).
The inspection reservation signal w for the confirmation wafer CW is received after the inspection reservation signal for the wafers W of the lot C have been received. Thus, after the wafers W of the lot C have been transferred in the bypassing manner, the confirmation wafer CW is transferred to the inspection module 11, and subjected to a confirmation inspection in the inspection module 11.
After the confirmation inspection using the confirmation wafer CW has been finished, the inspection module 11 resumes an inspection for wafers of a lot. In this example, it has been already determined that the wafers W of lots D and E are transferred in the skipping manner. Thus, from the wafers of lot F, the wafers are transferred to the inspection module 11 and subjected to an inspection in the inspection module 11.
Although the trouble of the inspection module 11 is resolved at the time point T5 so that the inspection module 11 becomes available in the course of taking out the wafers of lot C, lots D and E are transferred in the skipping manner. Namely, the wafer lots (i.e., the wafers in lots D and E) cannot be inspected.
An overlapping inspection module for performing an overlapping inspection is subjected to a periodic inspection (maintenance) once per day. During this periodic inspection, wafers W cannot be transferred to the overlapping inspection module. The periodic inspection is completed after the confirmation inspection of the overlapping module of a confirmation wafer CW is performed. Thus, there generates a similar problem. This problem is concretely described with reference to FIG. 12. Similarly to Fig. 11, a horizontal axis in FIG. 12 shows a time. The first row in FIG. 12 shows a timing at which a wafer is taken out from the wafer cassette 10 in the carrier block B1, and a timing at which a wafer is returned to the wafer cassette 10. The second row in FIG. 12 shows a process condition of the wafers in the overlapping inspection module, and the third row in FIG. 12 shows a transfer condition of wafers to the buffer module 12.
Also in this case, a first wafer in each of the lots A to F is taken out from the wafer cassette 10, an inspection reservation signal is outputted to the overlapping inspection module, In this example, an interval between a time point T13 and a time point T15 is the periodic inspection time. The periodic inspection includes a time required for a confirmation inspection for the overlapping inspection module of a confirmation wafer CW.
During the periodic inspection time for the overlapping module, the control part forbids an output of an inspection reservation signal for the wafers in a lot. Thus, in this example, no inspection reservation signal is outputted for the wafers of lots D and E that are brought out from the carrier block B1 during the periodic inspection time. Wafers W of the lots A to C whose inspection reservation signals haven been outputted (i.e., wafers to be transferred to the inspection module during the periodic inspection) are transferred in the bypassing manner. The wafers W of the lots D and E whose inspection reservation signals are not outputted are transferred in the skipping manner.
Since an inspection reservation signal w for the confirmation wafer CW is received after an inspection reservation signal c of lot C has been received by the overlapping inspection module, the confirmation wafer CW is transferred to the overlapping inspection module after the wafers of lot C have been transferred in the bypassing manner. Namely, in the course of transferring the lot D in the skipping manner, the confirmation wafer CW is transferred to the inspection module and subjected to a confirmation inspection. At the time when the confirmation wafer CW is unloaded from the inspection module upon completion of the confirmation inspection, the periodic inspection is completed. After the completion of the periodic inspection, the overlapping inspection module resumes an inspection for wafers of a lot. Thus, in this example, from the wafers of lot F. the wafers are inspected by the overlapping inspection module.
Therefore, in this example, although the overlapping inspection module becomes ready to receive the confirmation wafer CW, the confirmation wafer CW is transferred thereto after lot C has been transferred in the bypassing manner. Thus, there may occur a problem in that the start of the confirmation inspection is delayed, resulting in the elongation of the periodic inspection time. In addition, there may occur another problem in that, although the periodic inspection of the overlapping inspection module is finished at the time point T15, the wafers W of lots D and E are transferred in the skipping manner, whereby the wafer lots cannot be inspected.
Patent Document 1 describes a structure in which an inspection block including a plurality of inspection apparatuses is interposed between a cassette station and a process station. The system described therein performs a transfer control that is called a restart control in which a wafer is transferred from the cassette station to the process station through an inspection station, a processed wafer is returned to a carrier in a carrier station and temporarily received therein, and the wafer is transferred to the inspection station so as to inspect the wafer. However, since Patent Document 1 does not consider a case when the inspection apparatus has a trouble and/or how to control the transfer of the wafer during a maintenance operation of the inspection apparatus, the problem of the present invention cannot be solved even by the structure of the Patent Document 1.
Patent Document 1: JP2005-175052A